About Workshop:
Department: ECE
Topics Covered:
First Day:
- Introduction to Digital Image Processing
- Image Enhancement Techniques
- Histogram Equalization
- Edge Detection
- Image scrambling
- Lab: Hands on session of image processing algorithms
Second Day:
- Need of FPGAs for addressing high-performance DSP designs
- Introduction to Xilinx System Generator for DSP
- Concepts of system modeling using Simulink
- Overview of Xilinx block sets and system modeling for hardware implementation
- Model and simulate a DSP block using Simulink/ Xilinx System generator
- Lab: Getting started with Simulink
- Lab: Creating a 12 x 8 MAC Using the System Generator for DSP
- Lab: Signal Routing – custom system modeling for DSP applications
Third Day:
- Concepts of Hardware co-simulation using System Generator DSP
- Lab : Implementing a system controller as per the design specifications
- Lab : Designing a Multirate MAC FIR system
- Lab: Hardware co-simulation of FIR filter using Virtex-5 FPGA Evaluation platform
- Addressing Video and image processing applications using Xilinx FPGA’s –Challenges
- and current trends
- Lab: Demonstration of real time image processing application using Xilinx Spartan-6 &
- Virtex-5 FPGA Development platforms
- Receiving Registration Form on or before : 3rd April 2013
- Institute (Student): Rs. 2250
- Research scholars/Faculties: Rs. 3400
- Working professionals: Rs. 4500
Send Your Registration Form Along With DD to:
Mrs. R. Devaki,
VIT UNIVERSITY
Secretary, TIFAC CORE
Room No: 701, TT 7th floor,
Vellore-632009
Email: tifac@vit.ac.in,tifacvit@gmail.com
Phone No: 0416 – 2202381